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Reverse DC bias stress shifts in organic thin‐film transistors with gate dielectrics using parylene‐C
Author(s) -
Fukuda Kenjiro,
Suzuki Tatsuya,
Kumaki Daisuke,
Tokito Shizuo
Publication year - 2012
Publication title -
physica status solidi (a)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.532
H-Index - 104
eISSN - 1862-6319
pISSN - 1862-6300
DOI - 10.1002/pssa.201228219
Subject(s) - thin film transistor , materials science , parylene , crystallinity , gate dielectric , dielectric , threshold voltage , annealing (glass) , optoelectronics , dipole , transistor , electrical engineering , voltage , composite material , polymer , chemistry , organic chemistry , layer (electronics) , engineering
Abstract We have systematically investigated the reliability of organic thin‐film transistors (TFTs) using polychloro‐ p ‐xylylene (parylene‐C) as a gate dielectric material. The fabricated organic TFT devices exhibited positive bias shifts with negative DC gate‐source voltages; however, no hysteresis was observed in the transfer characteristics for the tested TFT devices. Moreover, this tendency was enhanced with increasing annealing temperatures, whereby X‐ray diffraction (XRD) results revealed that the crystallinity of the parylene‐C layers increased with thermal annealing. As a result the total dipole moments normal to the surface of the parylene‐C layers grew, which caused reverse bias shifts in the TFT devices.