Premium
Threshold voltage shift under electrical stress in amorphous, polymorphous, and microcrystalline silicon bottom gate thin‐film transistors
Author(s) -
Oudwan Maher,
Moustapha Oumkelthoum,
Abramov Alexey,
Daineka Dmitriy,
Bonnassieux Yvan,
Cabarrocas Pere Roca i
Publication year - 2010
Publication title -
physica status solidi (a)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.532
H-Index - 104
eISSN - 1862-6319
pISSN - 1862-6300
DOI - 10.1002/pssa.200925403
Subject(s) - thin film transistor , materials science , gate dielectric , subthreshold slope , optoelectronics , microcrystalline , silicon , amorphous silicon , oxide thin film transistor , dielectric , threshold voltage , amorphous solid , transistor , nanocrystalline silicon , strained silicon , electrical engineering , layer (electronics) , nanotechnology , crystalline silicon , voltage , crystallography , chemistry , engineering
The crucial influence of the interface between the gate dielectric and intrinsic layer has been studied in detail for amorphous silicon, polymorphous silicon and microcrystalline silicon bottom gate thin‐film transistors. We show that the electrical parameters of the TFTs depend directly on the quality of this interface, which can be strongly degraded by a vacuum break. A hydrogen plasma pretreatment of this interface greatly improves the electrical characterstics of polymorphous silicon TFTs, the mobility increases from 0.4 to 0.75 cm 2 /V s while their subthreshold slope decreases from 1 to 0.7 V/dec. Moreover, we show that these improvements also translate into more stable TFT characteristics. Finally, microcrystalline silicon TFTs show the best stability and a nitrogen‐plasma treatment of the dielectric improves their stability.