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2‐Mb SPRAM design: bi‐directional current write and parallelizing‐direction current read based on spin‐transfer torque switching
Author(s) -
Kawahara T.,
Takemura R.,
Miura K.,
Hayakawa J.,
Ikeda S.,
Lee Y. M.,
Sasaki R.,
Goto Y.,
Ito K.,
Meguro T.,
Matsukura F.,
Takahashi H.,
Matsuoka H.,
Ohno H.
Publication year - 2007
Publication title -
physica status solidi (a)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.532
H-Index - 104
eISSN - 1862-6319
pISSN - 1862-6300
DOI - 10.1002/pssa.200777120
Subject(s) - spin transfer torque , current (fluid) , torque , reading (process) , spin (aerodynamics) , computer science , transfer (computing) , power (physics) , voltage , electrical engineering , chip , bit (key) , quantum tunnelling , optoelectronics , scheme (mathematics) , materials science , physics , engineering , parallel computing , magnetization , mathematical analysis , computer security , mathematics , quantum mechanics , magnetic field , law , political science , thermodynamics
A 1.8 V 2‐Mb SPRAM (SPin‐transfer torque RAM) chip using 0.2‐μm logic process with MgO tunneling barrier cell is reviewed, which demonstrates the circuit technologies for potential low power non‐volatile RAM, or universal memory. This chip features: an array scheme with bit‐by‐bit bi‐directional current write to achieve proper spin‐transfer torque writing of 100‐ns, and parallelizing‐direction current reading with low voltage bit‐line that leads to 40‐ns access time. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)