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Review of methods for the mitigation of plasma‐induced damage to low‐dielectric‐constant interlayer dielectrics used for semiconductor logic device interconnects
Author(s) -
Miyajima Hideshi,
Ishikawa Kenji,
Sekine Makoto,
Hori Masaru
Publication year - 2019
Publication title -
plasma processes and polymers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.644
H-Index - 74
eISSN - 1612-8869
pISSN - 1612-8850
DOI - 10.1002/ppap.201900039
Subject(s) - materials science , dielectric , interconnection , semiconductor , plasma , optoelectronics , degradation (telecommunications) , low k dielectric , silicon , engineering physics , semiconductor device , nanotechnology , electronic engineering , computer science , layer (electronics) , engineering , computer network , physics , quantum mechanics
Abstract The developments in advanced interconnect technology for semiconductor logic devices for the mitigation of plasma‐induced damage to low‐dielectric‐constant (low‐k) materials, including fluorosilicate glass and carbon‐doped silicon oxide is reviewed. The chemical bond structures of low‐k materials are summarized to help mitigate the k value degradation caused by moisture uptake after plasma processes. Damage suppression is accomplished by integrating deposition chemistries, pattern etch transfer, and post‐etch cleaning technologies. On the basis of analyses results, a discussion on the bond engineering of low‐k materials and their degradation during plasma processing is given. Challenges facing low‐k interconnect technology are also addressed.