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High‐efficiency (19%) screen‐printed textured cells on low‐resistivity float‐zone silicon with high sheet‐resistance emitters
Author(s) -
Hilali Mohamed M.,
Nakayashiki Kenta,
Ebong Abasifreke,
Rohatgi Ajeet
Publication year - 2006
Publication title -
progress in photovoltaics: research and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 2.286
H-Index - 131
eISSN - 1099-159X
pISSN - 1062-7995
DOI - 10.1002/pip.688
Subject(s) - sheet resistance , common emitter , equivalent series resistance , materials science , screen printing , silicon , optoelectronics , electrical resistivity and conductivity , spreading resistance profiling , contact resistance , float glass , wafer , coating , composite material , layer (electronics) , electrical engineering , voltage , engineering
High‐efficiency 4 cm 2 screen‐printed (SP) textured cells were fabricated on 100 Ω/sq emitters using a rapid single‐step belt furnace firing process. The high contact quality resulted in a low series resistance of 0·79 Ωcm 2 , high shunt resistance of 48 836 Ωcm 2 , a low junction leakage current of 18·5 nA/cm 2 (n 2 = 2) yielding a high fill factor (FF) of 0·784 on 100 Ω/sq emitter. A low resistivity (0·6 Ωcm) FZ Si was used for the base to enhance the contribution of the high sheet‐resistance emitter without appreciably sacrificing the bulk lifetime. This resulted in a 19% efficient (confirmed at NREL) SP 4 cm 2 cell on textured FZ silicon with SP contacts and single‐layer antireflection coating. This is apparently higher in performance than any other previously reported cell using standard screen‐printing approaches (i.e., single‐step firing and grid metallization). Detailed cell characterization and device modeling were performed to extract all the important device parameters of this 19% SP Si cell and provide guidelines for achieving 20% SP Si cells. Copyright © 2005 John Wiley & Sons, Ltd.