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Defect engineering of p‐type silicon heterojunction solar cells fabricated using commercial‐grade low‐lifetime silicon wafers
Author(s) -
Chen Daniel,
Kim Moonyong,
Shi Jianwei,
Vicari Stefani Bruno,
Yu Zhengshan Jason,
Liu Shaoyang,
Einhaus Roland,
Wenham Stuart,
Holman Zachary,
Hallam Brett
Publication year - 2021
Publication title -
progress in photovoltaics: research and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 2.286
H-Index - 131
eISSN - 1099-159X
pISSN - 1062-7995
DOI - 10.1002/pip.3230
Subject(s) - monocrystalline silicon , wafer , materials science , getter , silicon , optoelectronics , passivation , carrier lifetime , heterojunction , open circuit voltage , grain boundary , solar cell , crystalline silicon , voltage , nanotechnology , electrical engineering , metallurgy , layer (electronics) , microstructure , engineering
In this work, we integrate defect engineering methods of gettering and hydrogenation into silicon heterojunction solar cells fabricated using low‐lifetime commercial‐grade p‐type Czochralski‐grown monocrystalline and high‐performance multicrystalline wafers. We independently assess the impact of gettering on the removal of bulk impurities such as iron as well as the impact of hydrogenation on the passivation of grain boundaries and B‐O defects. Furthermore, we report for the first time the susceptibility of heterojunction devices to light‐ and elevated temperature–induced degradation and investigate the onset of such degradation during device fabrication. Lastly, we demonstrate solar cells with independently verified 1‐sun open‐circuit voltages of 707 and 702 mV on monocrystalline and multicrystalline silicon wafers, respectively, with a starting bulk minority‐carrier lifetime below 40 microseconds. These remarkably high open‐circuit voltages reveal the potential of inexpensive low‐lifetime p‐type silicon wafers for making devices with efficiencies without needing to shift towards n‐type substrates.