Design of optimized high precision fractional‐N frequency synthesizer with low spur

This article presents a novel multimode cascaded frequency division structure for a low‐spur wide‐bandwidth fractional‐N frequency synthesizer. In order to reduce fractional spur, the new ∆‐∑ modulators are designed as a three‐order structure and each of them is composed of a three‐bit three‐order hybrid feedback ∆‐∑ modulator. Besides, a mixing phase‐locked loop structure is designed to effectively cancel out the VCO cross‐coupling path to reduce spur. The synthesizer implemented in a standard 0.18 μm CMOS process occupies a core area of 0.36 mm 2 and generates a frequency ranging from 3 to 6 GHz using 50 MHz~100 MHz oscillator input. Measured results indicate that the fractional spur is lower than −80 dBc and the resolution is higher than 0.001 Hz.