Simulation and implementation of CMOS 8:1 LC ‐tank injection‐locked frequency divider

This letter simulates and measures a wide locking range LC ‐resonator injection‐locked frequency divider (ILFD) designed in the TSMC 0.18 μm process. The balanced‐injection 8:1 ILFD uses a current‐mode design method with one 2:1 p‐core LC sub‐ILFD and one 4:1 n‐core LC sub‐ILFD with wide locking range. The 4:1 sub‐ILFD uses a 5‐turn symmetric octagonal inductor and two 4‐turn inter‐wound transformers and parasitic capacitors to build the LC ‐resonator. The primary and the secondary inductors in the 1:1 transformer are identical for simple design. At the core power consumption 9.537 mW and at the incident power of 0 dBm, the measured 8:1 locking range is 1.11 GHz, from the incident frequency 16.83 to 17.94 GHz. The whole CMOS die occupies an area of 0.931 × 1.2 mm 2 . The simulated 8:1 sub‐ILFD also has wide locking range.