Premium
A 4.6‐ GH z low‐phase‐noise differential common‐gate C lapp VCO with simplified common‐mode biasing
Author(s) -
Din Amad Ud,
Nghia Nguyen Tai,
Phan Huu Nhan,
Nguyen Khac Vu,
Lee JongWook
Publication year - 2017
Publication title -
microwave and optical technology letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.304
H-Index - 76
eISSN - 1098-2760
pISSN - 0895-2477
DOI - 10.1002/mop.30602
Subject(s) - voltage controlled oscillator , phase noise , transconductance , varicap , cmos , common gate , electrical engineering , materials science , dbc , biasing , inductor , common mode signal , transistor , voltage , topology (electrical circuits) , electronic engineering , engineering , physics , capacitance , digital signal processing , analog signal , electrode , quantum mechanics
We present a new differential Clapp voltage‐controlled oscillator (VCO) suitable for low‐voltage scaled‐down CMOS technology. For loss compensation, the Clapp VCO uses a common‐gate topology that provides higher transconductance than that of the conventional common‐drain configuration. To provide reliable start‐up condition for the Clapp VCO, a small inductor is added at the gate of a transistor in the common‐gate configuration. The new configuration also simplifies DC biasing while providing a suitable common‐mode point for varactor tuning. All of these features allow the Clapp VCO to operate under low‐voltage and low‐power conditions. The fabricated Clapp VCO using 0.18‐μm RFCMOS achieves an excellent phase noise performance of −121 dBc/Hz at a 1 MHz offset from 4.6 GHz. Under a supply voltage of 1.0 V and a power consumption of 4.2 mW, the figure‐of‐merit (FOM) is −188 dBc/Hz.