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An integrated K a‐band VCO and divide‐by‐4 frequency divider with 30.2% tuning range in 90‐nm CMOS
Author(s) -
Alsuraisry Hamed,
Cheng JenHao,
Li WeiTsung,
Tsai JengHan,
Huang TianWei
Publication year - 2017
Publication title -
microwave and optical technology letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.304
H-Index - 76
eISSN - 1098-2760
pISSN - 0895-2477
DOI - 10.1002/mop.30520
Subject(s) - voltage controlled oscillator , frequency divider , varicap , electrical engineering , phase noise , cmos , dbc , wideband , frequency multiplier , inductor , phase locked loop , microwave , current divider , voltage divider , voltage , engineering , materials science , physics , telecommunications , capacitance , quantum mechanics , electrode
This article presents a wideband phase‐locked loop (PLL) front‐end, which consists of a dual‐core voltage‐controlled oscillator (VCO) and a divide‐by‐four (D4) frequency divider in 90‐nm CMOS technology. The switched inductors and varactor banks are used to enhance the tuning range of VCO. The D4 frequency divider is a body‐biased injection‐locked frequency divider (ILFD) cascoded with source‐injection current mode logic (SICML) for wider locking range and lower power consumption. This PLL front‐end demonstrates a 30.2% frequency tuning range (FTR) from 23.6 to 32 GHz and a phase noise of −101.22 dBc/Hz at 5.86 GHz with 1 MHz offset frequency. The output power is higher than −15 dBm among the operating bandwidth. The dc power consumption is 40.8 mW at 1.2 V and 1.5 V supply voltages. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:1305–1309, 2017