Premium
A cascode linear power amplifier with reduced capacitance variation of common gate transistors
Author(s) -
Jeong Gwanghyeon,
Kang Seunghoon,
Joo Taehwan,
Hong Songcheol
Publication year - 2017
Publication title -
microwave and optical technology letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.304
H-Index - 76
eISSN - 1098-2760
pISSN - 0895-2477
DOI - 10.1002/mop.30237
Subject(s) - cascode , amplifier , common source , transistor , capacitance , cmos , electrical engineering , materials science , common gate , electronic engineering , optoelectronics , rf power amplifier , voltage , engineering , physics , electrode , quantum mechanics
A common‐gate (CG) transistor in a cascode power amplifier has a large input capacitance variation in the saturation region with respect to the source voltage. This causes large nonlinearity in a CMOS PA that utilizes a cascode configuration. Here, we propose a method to reduce the capacitance variation by introducing a parallel auxiliary transistor that works in both the saturation and depletion regions by applying a bias voltage that is slightly different from the main one. This provides the proposed CMOS PA a gain of 27.8 dB and an output power of 16.7 dBm with a PAE of 14.7% for an 802.11n modulated signal with an EVM of −25 dB. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:125–128, 2017