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A 5 GH z fully‐integrated low‐power phase‐locked loop using 0.18‐μm CMOS technology
Author(s) -
Tsai JengHan,
Huang ChuanJung,
Hsieh TseYi,
Huang ShaoWei
Publication year - 2016
Publication title -
microwave and optical technology letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.304
H-Index - 76
eISSN - 1098-2760
pISSN - 0895-2477
DOI - 10.1002/mop.29848
Subject(s) - voltage controlled oscillator , phase locked loop , phase noise , dbc , electrical engineering , varicap , frequency divider , cmos , amplifier , engineering , microwave , electronic engineering , materials science , voltage , physics , telecommunications , electrode , quantum mechanics , capacitance
A 5 GHz fully integrated low‐power phase‐locked loop (PLL) was designed and fabricated on 0.18‐μm CMOS process. To achieve low power consumption, the transformer feedback VCO and high speed true single phase clock (TSPC) divider were adopted. A rail‐to‐rail buffer amplifier was incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. In addition, dual varactor pairs were utilized to enlarge the tuning rage of the VCO while maintaining the low KVCO. The PLL achieved low power of 12.12 mW with good phase noise. The closed loop phase noises were −90.88 and −115.8 dBc/Hz at 100 kHz and 10 MHz frequency offsets. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1534–1537, 2016