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A 2.4‐GHz CMOS power amplifier with parallel‐combined transistors and selective adaptive biasing for wireless LAN applications
Author(s) -
Baek Seungjun,
Ryu Hyunsik,
Nam Ilku,
Jeong Minsu,
Kim BoEun,
Lee Ockgoo
Publication year - 2016
Publication title -
microwave and optical technology letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.304
H-Index - 76
eISSN - 1098-2760
pISSN - 0895-2477
DOI - 10.1002/mop.29810
Subject(s) - biasing , amplifier , cmos , electronic engineering , transistor , electrical engineering , power (physics) , voltage , computer science , engineering , physics , quantum mechanics
This paper proposes a fully integrated linear wireless LAN (WLAN) CMOS power amplifier (PA) with parallel‐combined transistors and selective adaptive biasing. An adaptive bias circuit is applied to one of the parallel‐combined transistors to take advantage of both the parallel‐combined transistor method and adaptive biasing at the target output power region. By using the proposed biasing, the linear output power can be maximized, resulting in a higher power added efficiency (PAE). The experimental results show that the fully integrated CMOS PA has a saturated output power of 26.9 dBm at 2.48 GHz with a PAE of 40.3% at a 3.3‐V supply voltage. The PA is also tested with the modulation and coding scheme 7 (MCS7) 802.11n signal (64‐QAM 65Mbps with 20MHz). It satisfies a −28 dB error vector magnitude (EVM) and spectrum mask requirements at an output power of 19.8 dBm with a PAE of 18.8% without applying pre‐distortion. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1374–1377, 2016