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A low loss double‐pole double‐throw switch in 65 nm CMOS for wigig applications
Author(s) -
Choi Sunkyu,
Son Juho,
Hong Seungpyo,
Shin GyongSeop,
Kim ChoulYoung
Publication year - 2014
Publication title -
microwave and optical technology letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.304
H-Index - 76
eISSN - 1098-2760
pISSN - 0895-2477
DOI - 10.1002/mop.28713
Subject(s) - insertion loss , materials science , return loss , cmos , optoelectronics , capacitance , electrical engineering , microstrip , microwave , transmission line , engineering , physics , telecommunications , antenna (radio) , electrode , quantum mechanics
This article presents a 60 GHz low insertion loss double‐pole double‐throw (DPDT) switch implemented in 65 nm standard CMOS process. To achieve the low insertion loss, various techniques are used such as the double‐well body‐floating, gate‐floating, high‐performance thin‐film microstrip line, resonating the capacitance of the off‐state transistor, and the transmission line based matching network. To achieve both high performance and small area, EM simulations are intensely performed to model passive components. The DPDT switch achieves insertion loss of less than 2.7 dB, and return loss of better than 10 dB over the 52–66 GHz band. The measured IIP3 is 18 dBm (simulated IP1dB is 11.4 dBm). The fabricated DPDT switch has an effective area of 0.073 mm 2 . © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2864–2867, 2014