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A low power and low in‐band phase noise W‐band frequency synthesizer in 65 nm CMOS
Author(s) -
Yixiao Wang,
Le Ye,
Congyin Shi,
Huailin Liao,
Ru Huang,
Yangyuan Wang
Publication year - 2014
Publication title -
microwave and optical technology letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.304
H-Index - 76
eISSN - 1098-2760
pISSN - 0895-2477
DOI - 10.1002/mop.28543
Subject(s) - dbc , phase noise , frequency synthesizer , frequency multiplier , phase locked loop , frequency divider , cmos , electrical engineering , direct digital synthesizer , microwave , offset (computer science) , materials science , optoelectronics , physics , engineering , electronic engineering , telecommunications , computer science , programming language
A fully integrated 79 to 87 GHz frequency synthesizer is proposed, which combines a W‐band push–push ×4 frequency multiplier and a K‐band divider‐less phase locked loop (PLL) with sampling phase detector. The circuit is verified in a standard 65 nm CMOS process. The frequency synthesizer consumes 54 mW totally, and the measured phase noise of divide‐by‐2 frequency is −100.1 and −106.2 dBc/Hz at 100 kHz and 1 MHz offset, respectively. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2014–2018, 2014
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