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Linearization of stacked‐fet RF CMOS power amplifier using diode‐integrated bias circuit
Author(s) -
Kong Jeongwoon,
Jeong Jinho
Publication year - 2013
Publication title -
microwave and optical technology letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.304
H-Index - 76
eISSN - 1098-2760
pISSN - 0895-2477
DOI - 10.1002/mop.27472
Subject(s) - cmos , biasing , electrical engineering , amplifier , gain compression , diode , optoelectronics , materials science , electronic engineering , engineering , voltage
Abstract In this article, the linearization circuit of stacked‐FET RF CMOS power amplifier (PA) is presented. The proposed diode‐integrated bias circuit provides the increasing DC gate bias current which allows the bottom FET in the tripled‐stacked FET to saturate at a higher power compared to the conventional bias circuit. The simulation shows that the proposed bias circuit can increase a 1‐dB gain compression point of the stacked‐FET PA with a higher efficiency. It is demonstrated from the measurement of the triple‐stacked CMOS PAs with W‐CDMA input signal that the proposed diode‐integrated bias circuit can reduce the spectrum regrowth and increase the average efficiency. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1011–1014, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27472