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A fully integrated 40‐GB/S CDR with eight‐phase VCO for optical fiber communication
Author(s) -
Chen Yingmei,
Yan Shuangchao,
Wang Zhigong,
Zhang Li,
Li Wei
Publication year - 2013
Publication title -
microwave and optical technology letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.304
H-Index - 76
eISSN - 1098-2760
pISSN - 0895-2477
DOI - 10.1002/mop.27248
Subject(s) - phase noise , voltage controlled oscillator , jitter , dbc , demultiplexer , electrical engineering , cmos , multiplexer , physics , phase detector , data recovery , electronic engineering , voltage , engineering , telecommunications , computer science , multiplexing , computer hardware
This article presents a fully integrated 40‐Gb/s phase locked clock and data recovery (CDR) circuit with 1:4 demultiplexer (DEMUX) in International Business Machines (IBM) 90‐nm CMOS technology.The CDR circuit incorporates a novel eight‐phase CL ladder filtering voltage‐controlled oscillator and a quarter rate bang‐bang phase detector. The 40‐Gb/s input data are sampled with eight parallel differential master‐salve flip‐flops every 12.5 ps and the 40‐Gb/s data are demultiplexed into four 10‐Gb/s outputs when the CDR circuit is phase locked. The recovered and frequency divided 10‐GHz clock has a phase noise of −101.01 dBc/Hz at 1 MHz offset and a peak to peak jitter of 3.4 ps. The CDR and 1:4 DEMUX consumes 72 mW from a 1.2 V supply excluding out buffers. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:170–173, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27248