Premium
Design of low voltage, low power CMOS low noise amplifier for 2.4 GHz wireless communications
Author(s) -
Huang ChienChang,
Ku KaiWei
Publication year - 2012
Publication title -
microwave and optical technology letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.304
H-Index - 76
eISSN - 1098-2760
pISSN - 0895-2477
DOI - 10.1002/mop.27214
Subject(s) - electrical engineering , low noise amplifier , pmos logic , nmos logic , cmos , low voltage , amplifier , engineering , electronic engineering , noise figure , voltage , transistor
In this letter, design of a low voltage, low power CMOS low noise amplifier (LNA) for 2.4 GHz wireless communications is presented by using TSMC 0.18‐μm technology. The current reused architecture is adapted to reduce the consumed current, while the supply voltage is set to 0.6 V to meet the low voltage requirement as well. To simplify the bias network designs under low voltage operations, NMOS and PMOS devices are used with three‐stage configuration to enhance the gain performance. The measured results of the designed LNA show 17.7 dB in gain and 3.9 dB in noise figure with 0.86 mW of power consumption. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2849–2852, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27214