A low‐chip area and low‐phase noise hybrid phase‐locked loop

A low‐chip area and low‐phase noise phase‐locked loop (PLL) combining fractional‐N and integer‐N modes operating at 2.4 GHz band is proposed and fabricated in TSMC 0.18‐μm CMOS process.The proposed PLL with a Gm‐boosted Colpitts voltage‐controlled oscillator improves phase noise and a hybrid design of different divider loops achieves fast lock. At 1.8 V supply voltage, the proposed PLL shows a wide tuning range from 2.14 to 2.36 GHz, corresponding to 9.7%, a phase noise of −119.3 dBc/Hz at an offset frequency of 1 MHz from the carrier frequency of 2.14 GHz, a power consumption of 17.3 mW, and an output power of −15.37 dBm. Including pads, the chip area only occupies 0.588 (0.87 × 0.67) mm 2 . © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2295–2300, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27082