Design and implementation of a 2.8‐dB insertion loss v‐band bandpass filter in 0.13‐μm cmos technology

In this article, we demonstrate a low‐insertion‐loss V‐band bandpass filter with two finite transmission zeros by 0.13‐μm CMOS technology. The proposed filter architecture has the following feature: The low‐frequency transmission‐zero (ω z 1 ) can be tuned individually by the series‐feedback capacitor C s and the series capacitor C 3 . After ω z 1 is determined by C s and C 3 , the high‐frequency transmission zero (ω z 2 ) can be tuned individually by the parallel‐feedback capacitor C p . Besides, low‐insertion‐loss is achieved by adopting thick microstrip‐line with optimized ground‐plane pattern as the needed inductors to minimize the metal and substrate loss. This filter achieves insertion‐loss (1/S 21 ) lower than 3 dB over the frequency range of 45–52 GHz, input return loss (S 11 ) better than −10 dB over the frequency range of 41.2–57.8 GHz, and output return loss (S 22 ) better than −10 dB over the frequency range of 39.5–55.9 GHz. The minimum insertion‐loss is 2.8 dB at 48 GHz, to the authors' knowledge, this is one of the best results ever reported for a V‐band CMOS bandpass filter in the literature. The chip area is only 0.295 × 0.21 mm 2 , i.e., 0.062 mm 2 , excluding the test pads and dummy metals for design rule requirement. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2001–2006, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26984