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A low‐power 5‐GHz CMOS RF receiver for WLAN applications
Author(s) -
Cha Minyeon,
Kwon Ickjin
Publication year - 2012
Publication title -
microwave and optical technology letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.304
H-Index - 76
eISSN - 1098-2760
pISSN - 0895-2477
DOI - 10.1002/mop.26700
Subject(s) - cmos , electrical engineering , noise figure , baseband , amplifier , rf front end , electronic engineering , microwave , radio frequency , engineering , radio receiver design , low power electronics , chip , direct conversion receiver , power (physics) , telecommunications , transmitter , physics , channel (broadcasting) , power consumption , quantum mechanics , detector
A low‐power 5‐GHz IEEE 802.11a CMOS RF receiver for wireless local area network is designed.For low‐power dissipation, a dual conversion current‐driven passive mixer is used in an RF front‐end. An optimum allocation of alternated low‐pass filters and amplifiers in a baseband analog chain is also performed. The receiver is fabricated in 0.13 μm 1‐poly 6‐metal CMOS technology. The fully integrated receiver achieves 90.5 dB maximum gain, 7.1 dB noise figure, and −20 dBm input‐referred third‐order intercept point. The chip area is 3.25 mm 2 and it consumes a power of 40.8 mW from a supply voltage of 1.2 V. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:842–847, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26700