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A 5.8‐GHz frequency synthesizer chip design for worldwide interoperability for microwave access application
Author(s) -
Huang JhinFang,
Shih ChunWei,
Liu RonYi
Publication year - 2011
Publication title -
microwave and optical technology letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.304
H-Index - 76
eISSN - 1098-2760
pISSN - 0895-2477
DOI - 10.1002/mop.26405
Subject(s) - voltage controlled oscillator , phase noise , electrical engineering , frequency synthesizer , dbc , wideband , electronic engineering , microwave , chip , cmos , engineering , capacitor , phase locked loop , voltage , telecommunications
A 5.8‐GHz frequency synthesizer using wideband LC‐tank voltage‐controlled oscillator (VCO) for worldwide interoperability for microwave access applications with a 1.8 V voltage supply has been designed and successfully implemented in TSMC 0.18 μm CMOS process. In this proposed circuit, two important ideas are applied. First, a 3‐bit binary weighted capacitor array in the VCO is adopted to extend the tuning range and reduce the phase noise. Second, a class‐AB current mode logic is utilized in first divider stage to handle the high frequency signal. Measured results show that output frequency of VCO is tunable from 5.3 to 6.1 GHz corresponding to 14.1%, and phase noise is −110.2 dBc/Hz at 1 MHz offset, output power spectrum is −9.24 dBm at frequency of 5.73 GHz, power consumption is 32 mW, and including pads, chip area is 0.53 (0.82 × 0.65) mm 2 . © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:2931–2935, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26405