A high‐SFDR direct digital frequency synthesizer with embedded error‐compensation CMOS OTP ROM for wireless receivers

A direct digital frequency synthesizer (DDFS) using on‐chip CMOS one‐time programmable read‐only memory (OTP ROM) is presented. A straight‐line approximation algorithm for sinusoid with compensation is adopted such that the accuracy could be maintained and the cost is reduced. Most important of all, a CMOS OTP ROM is used as a look‐up ROM table, which is implemented by a typical logic CMOS process. Therefore, the proposed DDFS can be integrated in any CMOS‐based front‐end circuit for wireless communication systems. The proposed DDFS design is fully implemented using a typical 1P6M 0.18 μm CMOS process. It has a 12‐bit amplitude resolution with 86.89 dB spurious free dynamic range using a small ROM size of 256 bits. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1695–1699, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24422