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A high‐performance wideband cmos low‐noise amplifier using inductive series and parallel peaking techniques
Author(s) -
Lee JenHow,
Chen ChiChen,
Lin YoSheng
Publication year - 2008
Publication title -
microwave and optical technology letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.304
H-Index - 76
eISSN - 1098-2760
pISSN - 0895-2477
DOI - 10.1002/mop.23338
Subject(s) - wideband , noise figure , electrical engineering , linearity , amplifier , cmos , low noise amplifier , bandwidth (computing) , return loss , electronic engineering , engineering , physics , telecommunications , antenna (radio)
A 1–11 GHz wideband low‐noise amplifier (LNA) with good phase linearity properties (group‐delay variation is only ±35.56 ps across the 3.1–10.6 GHz band of interest) using standard 0.18 μm CMOS technology is reported. To enhance the bandwidth for achieving both high and flat gain and small group‐delay variation, the inductive shunt‐peaking technique is adopted in the load of the input stage, while the inductive series‐peaking technique is adopted in the input terminal of the output stage. The wideband LNA dissipates 29.46 mW power and achieves input return loss (S 11 ) of −9.32 to −9.98 dB, flat forward gain (S 21 ) of 11 ± 1 dB, reverse isolation (S 12 ) of −46 to −60 dB, and noise figure of 4.15–4.85 dB over the 3.1–10.6 GHz band of interest. Good 1‐dB compression point ( P 1 dB ) of −14 dBm and input third‐order inter‐modulation point (IIP3) of −3 dBm are achieved at 6.4 GHz. The chip area is only 675 μm × 632 μm excluding the test pads. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1240–1244, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23338