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Optimization of cascode configuration in CMOS low‐noise amplifier
Author(s) -
Song Ickhyun,
Koo Minsuk,
Jung Hakchul,
Jhon HeeSauk,
Shin Hyungcheol
Publication year - 2008
Publication title -
microwave and optical technology letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.304
H-Index - 76
eISSN - 1098-2760
pISSN - 0895-2477
DOI - 10.1002/mop.23163
Subject(s) - cascode , noise figure , electrical engineering , cmos , electronic engineering , amplifier , engineering , low noise amplifier , common gate , transistor , figure of merit , noise (video) , computer science , physics , optoelectronics , voltage , artificial intelligence , image (mathematics)
In this paper, design consideration of the cascode configuration in low‐noise amplifiers (LNA) using 0.13‐μm CMOS technology is presented. Performance factors of LNAs such as signal power gain, noise factor, and power consumption are analytically expressed in device parameters from its small‐signal equivalent circuit. The effect of the common‐gate transistor in each performance factor is evaluated at the target frequency of 17‐GHz ISM band. At this frequency, power gain and noise factor are degraded, which result from the common‐gate transistor. Figure of merit of LNAs is also optimized. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 646–649, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23163