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Implementation of a low‐cost phase‐locked loop clock‐recovery module for 40‐Gb/s optical receivers
Author(s) -
Woo Dong Sik,
Kim Kang Wook,
Lim SangKyu,
Ko Jesoo
Publication year - 2006
Publication title -
microwave and optical technology letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.304
H-Index - 76
eISSN - 1098-2760
pISSN - 0895-2477
DOI - 10.1002/mop.21335
Subject(s) - jitter , phase locked loop , clock recovery , electronic engineering , pll multibit , clock signal , phase detector , cpu multiplier , signal (programming language) , computer science , transmission (telecommunications) , clock domain crossing , engineering , electrical engineering , synchronous circuit , voltage , programming language
A low‐cost, compact, high‐performance clock‐recovery (CR) module using a new phase‐locked loop (PLL) for 40‐Gb/s optical receivers is successfully designed and implemented. The newly implemented frequency detector in the PLL helps to reduce the current consumption and also extended the frequency‐capture range. The implemented PLL clock‐recovery module demonstrates advantages over the conventional open‐loop type clock‐recovery module with a DR filter by significantly improving clock jitter, thus reducing overall module cost, and allowing the possibility of providing a proper clock signal in the case of temporary loss of NRZ input signals. The CR module exhibits error‐free operation during a 30‐min BER test with a time‐division‐multiplexing (TDM) 40‐Gb/s transmission system. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 312–315, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21335