Premium
Effects of CMOS process fill patterns on spiral inductors
Author(s) -
Chen ChangLee
Publication year - 2003
Publication title -
microwave and optical technology letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.304
H-Index - 76
eISSN - 1098-2760
pISSN - 0895-2477
DOI - 10.1002/mop.10790
Subject(s) - inductor , capacitance , parasitic capacitance , spiral (railway) , cmos , microwave , electronic engineering , silicon on insulator , electrical engineering , materials science , engineering , optoelectronics , silicon , mechanical engineering , physics , telecommunications , electrode , quantum mechanics , voltage
Spiral inductors with various metal fill‐patterns under the spiral is fabricated with SOI CMOS technology and characterized up to 49 GHz. The impact of the fill on the inductor characteristics is found to be very small and changes can be attributed to the increase of parasitic capacitance. A simple model is proposed that can accurately estimate the increase of capacitance. A simple model is proposed that can accurately estimate the increase of capacitance by the fill. Design guidelines for optimizing fill patterns are recommended. © 2003 Wiley Periodicals, Inc. Microwave Opt Technol Lett 36: 462–465, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.10790