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Low power quadrature voltage controlled oscillator
Author(s) -
Jin Jie,
Tan Mingtao
Publication year - 2019
Publication title -
international journal of rf and microwave computer‐aided engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.335
H-Index - 39
eISSN - 1099-047X
pISSN - 1096-4290
DOI - 10.1002/mmce.21952
Subject(s) - nmos logic , pmos logic , electrical engineering , phase noise , transistor , cmos , voltage , negative resistance , materials science , voltage controlled oscillator , oscillation (cell signaling) , optoelectronics , physics , engineering , chemistry , biochemistry
In this article, a low voltage low power quadrature voltage controlled oscillator (QVCO) coupled by four P&N transistors is presented. First, a novel negative resistance inductance capacitor (LC) oscillator is described, the N‐metal oxide semiconductor (NMOS) and P‐metal oxide semiconductor (PMOS) transistors are in series with the LC tank in the direct‐current (DC) path, and they generate the required negative resistance to compensate the energy loss of the LC tank and maintain the steady oscillation of the oscillator. Then, based on two identical LC oscillators, four P&N transistors are used as coupling terminals to generate quadrature outputs. The proposed QVCO is designed and simulated with GlobalFoundries' 0.18 μm CMOS RF process. The Cadence IC design tools postlayout simulation results demonstrate that the oscillation frequency of the QVCO can be tuned from 2.0 to 5.6 GHz by adjusting the bias voltage, and the phase noise of the voltage controlled oscillator is −114 dBc/Hz at 1 MHz offset. Moreover, the proposed QVCO consumes only 2.31 mW from a 1.2 V supply voltage and it occupies a compact area of 0.45 mm 2 including the bond pads.