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A wideband two‐stage Doherty power amplifier at high back‐off by exploring feasible design space
Author(s) -
Ghosh Sujata,
Rawat Karun
Publication year - 2018
Publication title -
international journal of rf and microwave computer‐aided engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.335
H-Index - 39
eISSN - 1099-047X
pISSN - 1096-4290
DOI - 10.1002/mmce.21528
Subject(s) - amplifier , predistortion , doherty amplifier , adjacent channel power ratio , electronic engineering , linear amplifier , electrical engineering , wideband , bandwidth (computing) , power added efficiency , power bandwidth , rf power amplifier , computer science , engineering , telecommunications
This article explores a design space for bandwidth enhancement of two‐stage Doherty power amplifier for higher back‐off based on same devices. This design space analysis shows that for any back‐off level, a number of bandwidth enhancement solutions can be obtained with various combinations of design parameters for load combiner and load impedance. Therefore, the proposed scheme explores design space in terms of optimum design parameters for load combiner and load impedance for best bandwidth and realizability at a high back‐off. The proposed design methodology is validated with a two‐stage Doherty power amplifier using 25 W packaged Gallium Nitride High Electron Mobility Transistors. This Doherty power amplifier provides measured drain efficiency between 66% to 73.8% at saturation and 45% to 63.6% at 8‐9 dB output power back‐off from 1.7 to 2.025 GHz. Measurement with WCDMA signals shows that the adjacent channel power ratio is better than −46 dBc after applying digital predistortion.