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A multiband carrier generation architecture for UHF, 2.4 GHz, and 5 GHz ISM applications
Author(s) -
Oh NamJin
Publication year - 2009
Publication title -
international journal of rf and microwave computer‐aided engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.335
H-Index - 39
eISSN - 1099-047X
pISSN - 1096-4290
DOI - 10.1002/mmce.20335
Subject(s) - phase noise , voltage controlled oscillator , electrical engineering , cmos , dbc , microwave , ultra high frequency , local oscillator , polyphase system , wibro , radio frequency , electronic engineering , physics , engineering , telecommunications , voltage , wireless , wireless network , wireless broadband
Novel multiband carrier generation architecture is proposed that can be applicable for RFID reader, WLAN 802.11a‐b‐g, and ZigBee sensor network, and implemented with 0.18 μm CMOS technology. In the proposed architecture, a quadrature voltage controlled oscillator (QVCO) is implemented by coupling two differential cross‐coupled LC VCOs to generate in‐phase (I) and quadrature (Q) signals operating at one‐thirds of the 5 GHz frequency range. As well, the differential second harmonic signal of the VCO core frequency is generated by mixers, and then converted to I/Q signals via a single‐stage tunable polyphase filter. By single sideband mixing of the I/Q signals of the QVCO and the polyphase filter, a cleaner carrier signal can be generated in the frequency band of 5 GHz. By including extra frequency dividers, the architecture can also be reconfigured to generate UHF band and 2.4 GHz band. The proposed architecture draws about 32 mA including the QVCO core current consumption of 2.8 mA from 1.8 V supply. The measured tuning frequency of the QVCO core ranges from 1.57 to 1.84 GHz. The measured phase noise is −104.5 dBc/Hz at 1 MHz offset from 4.84 GHz. The chip layout occupies an area of 1.44 × 1.4 mm 2 on Si substrate, including the DC and RF pads. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.