Premium
Two‐stage degradation in n‐channel LTPS‐TFTs under negative and positive bias stresses
Author(s) -
Guo Jian,
Yu Zhig,
Yan Wei,
Shi Dawei,
Xue Jianshe,
Xue Wei
Publication year - 2020
Publication title -
journal of the society for information display
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.578
H-Index - 52
eISSN - 1938-3657
pISSN - 1071-0922
DOI - 10.1002/jsid.873
Subject(s) - materials science , degradation (telecommunications) , thin film transistor , polycrystalline silicon , threshold voltage , trapping , trap (plumbing) , stress (linguistics) , grain boundary , subthreshold conduction , channel (broadcasting) , silicon , voltage , optoelectronics , transistor , composite material , layer (electronics) , electronic engineering , electrical engineering , environmental science , biology , ecology , linguistics , philosophy , microstructure , environmental engineering , engineering
Device degradation behaviors of n‐channel low‐temperature polycrystalline silicon thin film transistors under negative bias stress and positive bias stress were investigated. It was found that the threshold‐voltage has a two‐stage degradation, shifting to different direction with time. The mobility and the subthreshold swing SS both show a dependence on the stress time. It was determined that the interface trap states, the grain boundary trap states, and electron trapping together dominate the time‐dependent degradation behaviors. The trap is caused by the rupture of Si─H and Si─O bonds. A comprehensive model is proposed to explain the time‐dependent degradation behaviors clearly. In addition, after removing the stress, the recovery behaviors of threshold voltage V th can be observed, which provide the evidence supporting the degradation model proposed.