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The new route for realization of 1‐μm‐pixel‐pitch high‐resolution displays
Author(s) -
Choi Ji Hun,
Yang JongHeon,
Pi JaeEun,
Hwang ChiYoung,
Kim YongHae,
Kim Gi Heon,
Kim HeeOk,
Hwang ChiSun
Publication year - 2019
Publication title -
journal of the society for information display
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.578
H-Index - 52
eISSN - 1938-3657
pISSN - 1071-0922
DOI - 10.1002/jsid.821
Subject(s) - pixel , dot pitch , realization (probability) , thin film transistor , channel (broadcasting) , transistor , line (geometry) , wafer , materials science , holography , computer science , resolution (logic) , optoelectronics , subthreshold conduction , image resolution , optics , electrical engineering , voltage , physics , telecommunications , artificial intelligence , engineering , nanotechnology , layer (electronics) , statistics , mathematics , geometry
A new pixel structure for the realization of a 1‐μm‐pixel‐pitch display was developed. This structure, named vertically stacked thin‐film transistor (VST), was based on the conventional back‐channel etched thin‐film transistor (TFT), but all the layers except the horizontal gate line were vertically stacked on the embedded data line, enabling the implementation of high‐resolution display panels. The VST device with a channel length of 1 μm showed a high field effect mobility of more than 50 cm 2 /Vs and low subthreshold slope of 78 mV per decade. It also shows a high uniform electrical characteristic over the entire 6‐in. wafer. The development of a new pixel architecture is expected to enable the implementation of 1‐μm‐pixel‐pitch high‐resolution displays such as spatial light modulators for digital holograms.