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A timing controller embedded driver IC with 3.24‐Gbps eDP interface for chip‐on‐glass TFT‐LCD applications
Author(s) -
Kim TaeJin,
Baek Changhoon,
Chun Sengsub,
Lee KilHoon,
Hwang JongIl,
Kwon Kyeonghwan,
Kim YongHun,
Park HyunSang,
Shin Youngmin,
Ryu Seongyoung,
Lee JaeYoul,
Hwang Gyoocheol,
Kim Gyeongnam
Publication year - 2016
Publication title -
journal of the society for information display
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.578
H-Index - 52
eISSN - 1938-3657
pISSN - 1071-0922
DOI - 10.1002/jsid.446
Subject(s) - computer science , liquid crystal display , cmos , power management , computer hardware , chip , interface (matter) , controller (irrigation) , voltage , embedded system , power (physics) , electronic engineering , electrical engineering , engineering , telecommunications , maximum bubble pressure method , agronomy , physics , bubble , quantum mechanics , parallel computing , biology , operating system
This paper presents a timing controller embedded driver (TED) IC with 3.24‐Gbps embedded display port (eDP), which is implemented using a 45‐nm high‐voltage CMOS process for the chip‐on‐glass (COG) TFT‐LCD applications. The proposed TED‐IC employs the input offset calibration scheme, the zero‐adjustable equalizer, and the phase locked loop‐based bang‐bang clock and data recovery to enhance the maximum data rate. Also, the proposed TED‐IC provides efficient power management by supporting advanced link power management feature of eDP standard v1.4. Additionally, the smart charge sharing is proposed to reduce the dynamic power consumption of output buffers. Measured result demonstrates the maximum data rate of 3.24 Gbps from a 1.1 V supply voltage with a 7.9‐inch QXGA 60‐Hz COG‐LCD prototype panel and 44% power saving from the display system.