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Fast estimation of RL‐loaded microelectronic interconnections delay for the signal integrity prediction
Author(s) -
Ravelo Blaise,
Eudes Thomas
Publication year - 2011
Publication title -
international journal of numerical modelling: electronic networks, devices and fields
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.249
H-Index - 30
eISSN - 1099-1204
pISSN - 0894-3370
DOI - 10.1002/jnm.838
Subject(s) - spice , signal integrity , interconnection , propagation delay , computer science , rlc circuit , transmission line , microelectronics , electronic engineering , transient (computer programming) , microstrip , electrical impedance , signal (programming language) , radio propagation , computation , capacitor , algorithm , telecommunications , electrical engineering , engineering , voltage , programming language , operating system
SUMMARY This article presents a modelling method of the signal delays induced by microelectronic interconnections regarding RL impedance load. The method proposed is based on the RLC model of the transmission lines (TL) extracted from the equivalent S parameters. Formulation for estimating the interconnection propagation delay is established according to the behaviour of the TL unit step responses. The second order model is validated with a microstrip interconnect prototype with simulations and measurements in frequency and time domains. The developed propagation delay model was validated with SPICE computations. For that, a transient simulation was performed by considering input signals corresponding to high‐speed data of some Gbits/s. Then, accurate results were found for interconnections with different lengths in order of millimetre and also by varying the load values. It was shown that the computed 50% propagation delays present of relative errors about 5%. Copyright © 2011 John Wiley & Sons, Ltd.