Simulation of the hot‐carrier degradation in short channel transistors with high‐K dielectric

The degradation produced by channel hot‐carrier (CHC) on short channel transistors with high‐k dielectric has been analyzed. For short channel transistors ( L <0.15 µm), the most damaging stress condition has been found to be V G = V D instead of the ‘classical’ V G = V D /2 determined for long channel transistors. In this work, experimentally validated simulations have been performed to demonstrate that this shift is not caused by the presence of the high‐k layer but due to short channel effects. Furthermore, the CHC degradation lifetime has been evaluated, revealing larger operating voltages for high‐k than for SiO 2 ‐based transistors. Copyright © 2010 John Wiley & Sons, Ltd.