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Simulation of the hot‐carrier degradation in short channel transistors with high‐K dielectric
Author(s) -
Amat E.,
Kauerauf T.,
Degraeve R.,
Rodríguez R.,
Nafría M.,
Aymerich X.,
Groeseneken G.
Publication year - 2010
Publication title -
international journal of numerical modelling: electronic networks, devices and fields
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.249
H-Index - 30
eISSN - 1099-1204
pISSN - 0894-3370
DOI - 10.1002/jnm.750
Subject(s) - transistor , degradation (telecommunications) , channel (broadcasting) , materials science , dielectric , optoelectronics , threshold voltage , voltage , electrical engineering , engineering
Abstract The degradation produced by channel hot‐carrier (CHC) on short channel transistors with high‐k dielectric has been analyzed. For short channel transistors ( L <0.15 µm), the most damaging stress condition has been found to be V G = V D instead of the ‘classical’ V G = V D /2 determined for long channel transistors. In this work, experimentally validated simulations have been performed to demonstrate that this shift is not caused by the presence of the high‐k layer but due to short channel effects. Furthermore, the CHC degradation lifetime has been evaluated, revealing larger operating voltages for high‐k than for SiO 2 ‐based transistors. Copyright © 2010 John Wiley & Sons, Ltd.