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An efficient neural network approach for nanoscale FinFET modelling and circuit simulation
Author(s) -
Alam M. S.,
Kranti A.,
Armstrong G. A.
Publication year - 2009
Publication title -
international journal of numerical modelling: electronic networks, devices and fields
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.249
H-Index - 30
eISSN - 1099-1204
pISSN - 0894-3370
DOI - 10.1002/jnm.715
Subject(s) - mosfet , capacitance , oscillation (cell signaling) , electronic engineering , amplifier , conductance , transistor , noise (video) , topology (electrical circuits) , electrical engineering , cmos , physics , optoelectronics , voltage , materials science , computer science , engineering , chemistry , condensed matter physics , electrode , quantum mechanics , biochemistry , artificial intelligence , image (mathematics)
The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano‐circuit simulation. The FinFET used in this work is designed using careful engineering of source–drain extension, which simultaneously improves maximum frequency of oscillation ƒ max because of lower gate to drain capacitance, and intrinsic gain A V 0 = g m / g ds , due to lower output conductance g ds . The framework for the ANN‐based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I d on drain–source V ds and gate–source V gs is derived by a simple two‐layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low‐noise amplifier. At low power ( J ds ∼10 µA/µm) improvement was observed in both third‐order‐intercept IIP 3 (∼10 dBm) and intrinsic gain A V 0 (∼20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first‐order to third‐order derivative of I d with respect to gate voltage and lower g ds in FinFET compared to bulk MOSFET. Copyright © 2009 John Wiley & Sons, Ltd.