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Numerical analysis on thermal characteristics for chip scale package by integrating 2D/3D models
Author(s) -
Yang Ping,
Li Wei
Publication year - 2008
Publication title -
international journal of numerical modelling: electronic networks, devices and fields
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.249
H-Index - 30
eISSN - 1099-1204
pISSN - 0894-3370
DOI - 10.1002/jnm.694
Subject(s) - flip chip , stress (linguistics) , quad flat no leads package , reliability (semiconductor) , chip scale package , chip , printed circuit board , scale (ratio) , mechanical engineering , deformation (meteorology) , enhanced data rates for gsm evolution , soldering , materials science , substrate (aquarium) , temperature cycling , integrated circuit packaging , stress–strain curve , thermal , computer science , engineering , composite material , electrical engineering , physics , philosophy , adhesive , linguistics , oceanography , telecommunications , power (physics) , layer (electronics) , quantum mechanics , meteorology , geology
Abstract The objective of this paper is to investigate stress and strain of a special scale package‐substrate on chip for reliability evaluation or manufacture strategy in deep‐seated situation. A two‐dimensional model with one‐half of cross‐section (2D model) and a three‐dimensional model with one‐fourth of whole package (3D model) were built, respectively, to simulate the thermal stress and strain of CSP‐SOC under the condition of the standard industry thermal cycling temperature −40 to125°C. The different locations can be processed by using the two models, respectively, based on different modeling simplified modes. By using 2D model, the numerical simulation shows that the maximum deformation of the prototype occurs in printed circuit board (PCB), the maximum stress and strain occurs in the outer solder balls. In the meantime, by the results of 3D model, the simulation shows that the maximum elastic strain occurs in the interface between the solder balls and PCB, the minimum strain occurs in the underfill tape, the maximum packaging stress occurs in the edge area of the chip. The result from 3D model maybe more impersonal to reflect the stress and strain characteristics because the third direction is considered in modeling. The analysis by integrating the 2D model and 3D model can get a more comprehensive profile for the thermal investigation of chip scale package (CSP) than by using any single model. The investigation built a basis for improving reliability in engineering design of CSP product. Copyright © 2008 John Wiley & Sons, Ltd.