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Wide‐band modelling of CMOS interconnections and voiding damages with the lumped element LE‐FDTD method
Author(s) -
Alimenti F.,
Impronta M.,
Scorzoni A.,
Roselli L.
Publication year - 2004
Publication title -
international journal of numerical modelling: electronic networks, devices and fields
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.249
H-Index - 30
eISSN - 1099-1204
pISSN - 0894-3370
DOI - 10.1002/jnm.557
Subject(s) - finite difference time domain method , interconnection , cmos , electronic engineering , stack (abstract data type) , computer science , engineering , physics , optics , telecommunications , programming language
Abstract This paper illustrates the application of a lumped element‐finite difference time domain (LE‐FDTD) simulator to the wide‐band modelling of CMOS interconnections. To achieve very accurate results the short‐open calibration (SOC) technique has been adopted. Specific parameters of a CMOS interconnection laterally screened by a stack of metal vias have been extracted in the two cases of an unperturbed and a purposely damaged metal line. The behaviour of void‐like defects in the metal line has been also studied using the fully three‐dimensional capabilities of the simulator. It has been demonstrated that, at least in the simulated cases, only the specific resistance is affected by damaging. Copyright © 2004 John Wiley & Sons, Ltd.