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An ultra‐low‐power CNFET ‐based improved Schmitt trigger design for VLSI sensor applications
Author(s) -
Vidhyadharan Abhay Sanjay,
Vidhyadharan Sanjay
Publication year - 2021
Publication title -
international journal of numerical modelling: electronic networks, devices and fields
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.249
H-Index - 30
eISSN - 1099-1204
pISSN - 0894-3370
DOI - 10.1002/jnm.2874
Subject(s) - schmitt trigger , cmos , very large scale integration , computer science , electronic circuit , electronic engineering , power (physics) , electrical engineering , voltage , embedded system , engineering , physics , quantum mechanics
To enable easy integration of Internet of Things (IoT) sensors with digital very large scale integrtaion (VLSI) circuits, the interface circuits need to operate efficiently even at low power supply voltages, consuming minimum power from the limited onboard supply source. Schmitt triggers have higher noise margins and lower delays as compared to conventional static CMOS logic circuits, at low‐voltage levels and hence are being widely used in VLSI sensor applications. Carbon nanotube FETs (CNFETs) have I ON : I OFF and I ON : C GG ratios significantly greater than the corresponding CMOS devices, and hence they have been acknowledged as viable candidates to replace CMOS devices in ultra‐low‐power VLSI circuits. This article presents an ultra‐low‐power CNFET‐based Schmitt trigger design, which consumes significantly lower power than the conventional design. The cause of the higher power consumption in conventional CMOS‐based Schmitt trigger is the availability of a direct path between V DD and ground for a longer time duration, during switching. The short‐circuit path in the conventional CMOS Schmitt trigger circuit is the result of the design methodology adopted to obtain hysteresis in VTC curve. The threshold voltage of the CNFET can be easily configured by an appropriate selection of its chiral vector. This property of the CNFET has been used in the implementation of a new, simple but effective Schmitt trigger, which minimizes the short‐circuit currents, while providing the same hysteresis as that of conventional design. The proposed circuit operates at 0.4 V V DD to cater for low‐voltage levels of VLSI sensor applications. The proposed CNFET‐based Schmitt trigger consumes only 0.002 times the power of conventional CMOS Schmitt trigger and operates 56 times faster than the conventional CMOS design. The overall PDP in the proposed CNFET‐based Schmitt trigger has been demonstrated to be merely 0.0003% of the PDP in corresponding conventional designs.