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Contact engineered charge plasma junctionless transistor for suppressing tunneling leakage
Author(s) -
Kumar Harendra,
Singh Sangeeta,
Priyadarshani Kumari Nibha,
Ghosh Jayanta,
Naugarhiya Alok
Publication year - 2020
Publication title -
international journal of numerical modelling: electronic networks, devices and fields
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.249
H-Index - 30
eISSN - 1099-1204
pISSN - 0894-3370
DOI - 10.1002/jnm.2812
Subject(s) - quantum tunnelling , materials science , optoelectronics , transistor , leakage (economics) , schottky barrier , electrical engineering , silicon , contact resistance , nanotechnology , voltage , engineering , layer (electronics) , diode , economics , macroeconomics
This work reports contact engineered charge plasma junctionless transistor (CE‐CP‐JLT) to suppress the tunneling leakage current by deploying calibrated exhaustive 2‐D TCAD simulations. This analysis considered the detrimental effect due to the nonohmic source and drain side contacts by including universal Schottky tunneling and band‐to‐band tunneling models. Our study suggests to reduce the source/drain metal contacts to control the carriers tunneling in OFF state. This contact engineering can effectively minimizes the leakage with retained drive current capabilities. This would in turn improve the device switching behavior and I ON / I OFF current ratio at least by four orders. The reduction in leakage current leads to decrease in static power consumption. This facilitates the CE‐CP‐JLT deployment in a portable device for longer duration with same power supply. Further, the device sensitivity analysis with respect to electrode contact length, gate oxide thickness, dielectric constant, channel length and silicon film thickness is also analyzed. Moreover, the comparative analysis of device analog behavior is also carried out here.