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A nonlinear feed‐forward memory‐less model to fast prediction of threshold voltage in junction‐less double‐gate MOSFETs
Author(s) -
Annabestani Mohsen,
Nasserian Mahshid,
Hasanzadeh Fatemeh,
TaherzadehSani Mohammad,
Hassanzadeh Alireza
Publication year - 2020
Publication title -
international journal of numerical modelling: electronic networks, devices and fields
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.249
H-Index - 30
eISSN - 1099-1204
pISSN - 0894-3370
DOI - 10.1002/jnm.2803
Subject(s) - threshold voltage , drain induced barrier lowering , mosfet , voltage , nonlinear system , transistor , double gate , function (biology) , electronic engineering , electrical engineering , computer science , control theory (sociology) , physics , engineering , quantum mechanics , control (management) , evolutionary biology , artificial intelligence , biology
Decreasing Drain‐Induced‐Barrier‐Lowering (DIBL) is one of the nondesirable short‐channel effects, causes the threshold voltage of the transistor to be reduced by increasing the drain voltage. DIBL makes it impossible for engineers to consider V T as a constant, and it is necessary to calculate V T as a function of the drain voltage. Therefore, to consider the DIBL effect in the design of ICs, a large computational burden is imposed on the system, which slows down the simulation process in circuit‐level simulators. Accordingly, a Nonlinear Feed‐Forward Memory‐Less (NFFML) model using the Gram‐Schmidt orthogonalization approach is proposed, which calculates the V T of the new generation of MOSFETs, that is, Junctionless Double‐Gate MOSFETs (JL‐DG‐MOSFETs), with high precision and a significant speed‐up in the computation of the model. It is shown that the proposed numerical method is 313 times faster than the state‐of‐the‐art analytical model. The normalized MSE is 0.435% on average, showing that the proposed approach can be a fast and accurate candidate for replacing the analytical modeling.