A  SPICE  model of  p ‐channel silicon tunneling field‐effect transistors for logic applications | Zendy

Woo Sola | Zendy; Jeon Juhee | Zendy; Kim Sangsig | Zendy

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A SPICE model of p ‐channel silicon tunneling field‐effect transistors for logic applications

Author(s) -

Woo Sola,

Jeon Juhee,

Kim Sangsig

Publication year - 2020

Publication title -

international journal of numerical modelling: electronic networks, devices and fields

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.249

H-Index - 30

eISSN - 1099-1204

pISSN - 0894-3370

DOI - 10.1002/jnm.2793

Subject(s) - spice , nand gate , logic gate , inverter , transistor , nand logic , field effect transistor , quantum tunnelling , electronic engineering , optoelectronics , electrical engineering , physics , engineering , voltage

In this study, we propose a SPICE model of p ‐channel silicon tunneling field‐effect transistors (TFETs) for logic applications. To verify our model, electrical characteristics of fabricated p ‐TFETs are calibrated by utilizing TCAD and SPICE simulations. We simulate various logic gates, such as complementary TFET ( c ‐TFET) inverters, c ‐TFET NAND gates, and c ‐TFET NOR gates using our TFET model. Our simulation shows that a c ‐TFET inverter can be operated at V DD as low as 0.3 V and that c ‐TFET logic gates based on our model can operate ~1000 times higher frequency than conventional TFET logic gates.

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