Premium
A systematic study of device structure on DC and small‐signal characteristics of millimeter‐wave AlGaN/GaN HEMT
Author(s) -
Mi Minhan,
Ma Xiaohua,
Yang Ling,
Zhang Meng,
Wu Sheng,
Hao Yue
Publication year - 2019
Publication title -
international journal of numerical modelling: electronic networks, devices and fields
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.249
H-Index - 30
eISSN - 1099-1204
pISSN - 0894-3370
DOI - 10.1002/jnm.2623
Subject(s) - materials science , passivation , optoelectronics , parasitic element , capacitance , time dependent gate oxide breakdown , signal (programming language) , parasitic capacitance , and gate , high electron mobility transistor , electrical engineering , gate oxide , channel (broadcasting) , transistor , voltage , layer (electronics) , electrode , physics , engineering , computer science , nanotechnology , quantum mechanics , programming language
In this paper, the relationship between the gate structure, passivation structure, short‐channel effect, source‐drain distance, DC, and the small‐signal characteristic of a device is studied through simulations. By studying the gate structure and passivation layer, it is concluded that the operating frequency of a device increases as the gate length decreases. However, as the gate length decreases, the gate resistance becomes the main factor restricting the small‐signal performance. In order to solve the contradiction between the gate resistance and gate length, a T‐shaped gate structure is studied, in which the gate height, gate cap, and passivation layer thickness are optimized. It is found that when the gate height and gate cap are 120 and 500 nm, respectively, the parasitic capacitance introduced by the gate cap can be minimized. Meanwhile, the influence of gate resistance on the small‐signal gain can also be reduced. Besides, the short‐channel effect is analyzed, and the scheme for improving the short‐channel effect is proposed. By analyzing the source‐drain distance, and considering the influence of parasitic capacitance and resistance on the small‐signal characteristic, the gate‐source spacing is determined to be 0.9 μm. The design of a gate‐drain spacing is mainly based on the influence of a breakdown voltage; therefore, the gate‐drain spacing should be 1.5 to 2 μm.