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FPGA implementation of chaos‐based high‐speed true random number generator
Author(s) -
Gupta Ramji,
Pandey Alpana,
Baghel Rajendra Kumar
Publication year - 2019
Publication title -
international journal of numerical modelling: electronic networks, devices and fields
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.249
H-Index - 30
eISSN - 1099-1204
pISSN - 0894-3370
DOI - 10.1002/jnm.2604
Subject(s) - field programmable gate array , nist , random number generation , ring oscillator , computer science , cryptography , gate array , embedded system , chaotic , generator (circuit theory) , 8 bit , computer hardware , block (permutation group theory) , electronic engineering , engineering , power (physics) , mathematics , algorithm , physics , geometry , cmos , quantum mechanics , artificial intelligence , natural language processing
A true random number generator (TRNG) is a basic building block of many modern cryptographic systems. As field programmable gate array (FPGA) has a flexible architecture and low‐cost test cycle, hence, it becomes an ideal platform for hardware implementation of digital systems. This paper presents an FPGA implementation of a high‐speed TRNG that is based on a chaotic oscillator at 100 MHz frequency with speed of 1600 Mbps. The experimental results show that the proposed generator is faster and more compact than the existing chaotic ring‐oscillator‐based TRNGs, and further, it is verified that the generated bit sequences pass all TRNG tests in National Institute of Standards and Technology (NIST SP 800‐22). The proposed TRNG is implemented in two FPGA families: Nexys 4 DDR XC7A100TCSG‐1 (Artix 7) and Basys 3 XC7A35T1CPG236C (Artix 7) Xilinx Vivado v.2017.3 design suite.