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Threshold voltage modeling for dual‐metal quadruple‐gate (DMQG) MOSFETs
Author(s) -
Samoju Visweswara Rao,
Tiwari Pramod Kumar
Publication year - 2015
Publication title -
international journal of numerical modelling: electronic networks, devices and fields
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.249
H-Index - 30
eISSN - 1099-1204
pISSN - 0894-3370
DOI - 10.1002/jnm.2126
Subject(s) - threshold voltage , drain induced barrier lowering , reverse short channel effect , materials science , overdrive voltage , voltage , metal gate , optoelectronics , mosfet , transistor , gate oxide , field effect transistor , charge (physics) , electrical engineering , condensed matter physics , physics , engineering , quantum mechanics
Summary In this paper, a three‐dimensional (3D) model of threshold voltage is presented for dual‐metal quadruple‐gate metal‐oxide‐semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge (Q inv ) at the ‘virtual‐cathode’ reaches to a critical charge Q th . The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross‐section, oxide thickness, and gate length ratio. Further, the drain‐induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd.