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Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regime
Author(s) -
Rana Ashwani K.
Publication year - 2015
Publication title -
international journal of numerical modelling: electronic networks, devices and fields
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.249
H-Index - 30
eISSN - 1099-1204
pISSN - 0894-3370
DOI - 10.1002/jnm.2099
Subject(s) - mosfet , subthreshold conduction , subthreshold slope , electronic circuit , leakage (economics) , transistor , logic gate , materials science , optoelectronics , field effect transistor , and gate , very large scale integration , electrical engineering , gate dielectric , gate oxide , drain induced barrier lowering , electronic engineering , computer science , engineering , voltage , economics , macroeconomics
In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐ k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐ k dielectric (high‐ k ) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.