Gate leakage currents model for FinFETs implemented in Verilog‐A for electronic circuits design

ABSTRACT Because different conduction mechanisms can dominate the gate and drain/source leakage currents, mainly depending on the insulating materials used as gate dielectric, the dimensions of the gate structure, and the transistor operation regime, we proposed an improved analytical model to describe the behavior of these currents in silicon on insulator fin‐shaped field‐effect transistor devices by taking into account changes in the aforementioned factors. This model considers the direct tunneling, trap‐assisted tunneling, and band‐to‐band tunneling as the predominating mechanisms for leakage currents associated with the gate structure. These specific features make the model valid for a wide operation range and include its impact on the drain leakage current. The implementation of this model in Verilog‐A code is presented in this work, which allows calculating quickly and accurately the scaling constraint of a specific gate dielectric material and the power consumption that yields such leakage currents in a circuit by using commercial simulators. All presented results are validated with experimental data from fin‐shaped field‐effect transistors with different dimensions and gate dielectric materials and performed under different bias conditions. Copyright © 2014 John Wiley & Sons, Ltd.