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A surface‐potential‐based model for silicon nanowire junctionless field‐effect transistors including interface traps
Author(s) -
Deng Ye,
Fan Xiaoya,
Han Ru,
Li Cong
Publication year - 2014
Publication title -
international journal of numerical modelling: electronic networks, devices and fields
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.249
H-Index - 30
eISSN - 1099-1204
pISSN - 0894-3370
DOI - 10.1002/jnm.1985
Subject(s) - materials science , interface (matter) , trap (plumbing) , transistor , nanowire , subthreshold slope , doping , optoelectronics , silicon , subthreshold conduction , field effect transistor , reliability (semiconductor) , silicon nanowires , nanotechnology , electrical engineering , physics , voltage , power (physics) , composite material , capillary number , quantum mechanics , capillary action , meteorology , engineering
SUMMARY Interface trap is directly related to the electrical characteristics and reliability of the transistor, and it is an important factor affecting the performance of the device. This paper presents an analytic surface‐potential‐based model for cylindrical silicon nanowire junctionless field‐effect transistors (Si‐NW JLFET) including interface traps. In this paper, the proposed model is applicable to all Si‐NW JLFET working region including different interface trap charges with several nanowire radii and doping concentrations. Simulation results show that interface trap charges present two properties (positive or negative) depending on the different positions of the Fermi level in band gap, which have a significantly influence on the surface potential to cause junctionless transistor subthreshold degradation and flatband shifting. In addition, appropriate device parameters can effectively reduce the impact to the characteristic of the device made by the interface trap without degrading the performance of device. Copyright © 2014 John Wiley & Sons, Ltd.