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The 2‐D boundary element techniques for capacitance extraction of nanometer VLSI interconnects
Author(s) -
Zhai Kuangya,
Yu Wenjian
Publication year - 2013
Publication title -
international journal of numerical modelling: electronic networks, devices and fields
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.249
H-Index - 30
eISSN - 1099-1204
pISSN - 0894-3370
DOI - 10.1002/jnm.1934
Subject(s) - solver , boundary element method , capacitance , gaussian elimination , computational science , discretization , boundary (topology) , finite element method , computer science , speedup , computation , boundary value problem , parallel computing , algorithm , mathematics , mathematical analysis , gaussian , physics , mathematical optimization , engineering , structural engineering , electrode , quantum mechanics
SUMMARY This paper presents several techniques to accelerate the two‐dimensional (2‐D) direct boundary element method (BEM) for the capacitance extraction of nanometer very large‐scale integrated interconnects. Among these techniques, the nonuniform discretization technique minimizes the number of unknowns needed for accurate computation. The technique of adding virtual dielectric interface increases the sparsity of the coefficient matrix. With the technique of blocked Gaussian elimination, the memory usage and CPU time for solving the linear equation system are largely reduced. The analytical primitive functions for the 2‐D boundary integrals are also presented. Numerical results show that the presented techniques largely accelerate the 2‐D boundary element method. And finally, our BEM‐based capacitance solver demonstrates five times speedup over an advanced capacitance solver based on finite difference method. Copyright © 2013 John Wiley & Sons, Ltd.