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Error bounds for reduction of multi‐port resistor networks
Author(s) -
Ugryumova M. V.,
Rommes J.,
Schilders W. H. A.
Publication year - 2013
Publication title -
international journal of numerical modelling: electronic networks, devices and fields
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.249
H-Index - 30
eISSN - 1099-1204
pISSN - 0894-3370
DOI - 10.1002/jnm.1881
Subject(s) - resistor , reduction (mathematics) , computer science , port (circuit theory) , interconnection , algorithm , topology (electrical circuits) , electronic engineering , mathematics , electrical engineering , telecommunications , engineering , voltage , geometry
SUMMARY The interconnect layouts of chips can be modeled by large resistor networks. In order to be able to speed up simulations of such large networks, reduction techniques are applied to reduce the size of the networks. For some class of networks, an existing reduction strategy does not provide sufficient reduction in terms of the number of resistors appearing in the final network. In this paper, we propose an approach for obtaining a further reduction in the amount of resistors. The suggested approach improves sparsity of the conductance matrix by neglecting resistors that do not contribute significantly to the behavior of the circuit. Explicit error bounds, which give an opportunity to control the errors due to approximation, have been derived. Numerical examples show that the suggested approach appears promising for multi‐terminal resistor networks, and in combination with the existing reduction strategy, leads to better reduction. Copyright © 2013 John Wiley & Sons, Ltd.